The Snickerdoodle Book/HardwareArchitecture
- 1 Hardware Architecture
- 1.1 1. Overview
- 1.2 2. Connectors
- 1.3 3. Power Supplies
- 1.4 4. Zynq AP SoC Architecture
- 1.5 5. Zynq Configuration
- 1.6 6. DDR Memory
- 1.7 7. microSD Slot
- 1.8 8. Wireless
- 1.9 9. Platform Controller (STM32)
- 1.10 10. Crypto-Authentication Device
|Snickerdoodle One||Snickerdoodle Black|
|Chipset||Xilinx® Zynq® -7010||Xilinx® Zynq® -7020|
|CPU||32-Bit dual-core ARM® Cortex™-A9 w/640kB cache and dual 128-bit NEON™coprocessors|
|Performance||3335 DMIPS/2668 MFLOPS @ 667MHz||4330 DMIPS/3464 MFLOPS @ 866MHz|
|Flash||16 MB XIP NOR and up to 200 GB SDIO NAND via captive microSD card cage|
|DRAM||512MB @ 400MHz LPDDR2||1GB @ 400MHz LPDDR2||1 GB @ 25.6 Gbps|
|SRAM||256 kB @ 28.4 Gbps||256 kB @ 36.9 Gbps|
TODO: continue copying Table 1.1 from The Snickerdoodle Book.
Snickerdoodle is a compact, modular, highly-integrated embedded development platform that combines powerful processing capability with wireless connectivity and flexible configurability. Snickerdoodle utilizes a Xilinx Zynq-7000 series All-Programmable SoC which combines a dual-core ARMCortex-A9 processor with a Xilinx 7-Series FPGA. The ARM core provides a well known architecture for application development and is an ideal target for an embedded Linux system. The tightly-integrated FPGA fabric allows for connection with a wide variety of peripheral devices as well as the realization of custom logic for high-speed application-specific processing. Snickerdoodle comes with either a Zynq Z-7010 or a more powerful Zynq Z-7020 available as an optional upgrade.
InfoBox: J2 is a Samtec TFM-115-01-F-DA/ SFM-115-L1-F-D-A. J3, JA1, JA2, JB1, JB2 and JC1 are Samtec TFM- 120-01-F-D-A/SFM-120-L1-F-D-A
The USB power input and serial console are both accessed using the USB micro-B receptacle, designated J1. Power input is described in more detail in Chapter 3 . The most notable connectors on Snickerdoodle are the 0.050 in. double row headers. There are two possible connector orientations:
VocabBox: TFM - Top-facing shrouded male terminal header VocabBox: SFM - Bottom-facing female socket strip
CautionBox: The pin numbering appears as a mirror image between the TFM and SFM connectors as they are intended to be mounted on opposite sides of the board. This pin numbering is reflected in all tables in this manual.
Figure 2.2 shows a male pin configuration mounted on the top-side of the board for easy access with wire-to-board connectors. Female connectors mounted on the bottom side of the board can be used for modular connection to baseboards. Table 2.1 shows the connectors and their descriptions.
TODO: insert Table 2.1
Processor Subsystem Connectivity
External connection to the processor subsystem (PS) is done through J3 and provides access to multiplexed input/output (MIO). By default, the MIO pins connected to J3 are configured as GPIO by the FSBL and the configuration is carried through U-Boot before being handed off to Linux at boot time. The configuration of these pins can be changed to utilize additional peripheral interfaces including Ethernet, USB host, UART, SPI, CAN and I2C. The configuration of the PS and the pinout of the connector is illustrated in Figure B.6 .
TODO: insert link to Figure B.6.
Figure 2.4 shows the unallocated MIO pin configuration for the Snickerdoodle default board preset. MIO[16:39] are connected to J3 and can be customized for application specific connections. Changes to the processing subsystem initialization (i. e., FSBL, U-Boot) and the devicetree must be made for any customizations made to the MIO configuration.
WarningBox: Care must be taken when connecting to the FPGA system as the pins can be reconfigured to a variety of input and output types.
The versatility and flexibility of Snickerdoodle is due to the integrated FPGA fabric built into the SoC. The power of the FPGA is made available on five dedicated connectors. Electrically, the connections available on these connectors have the ability to accept and generate a variety of signals; all specified in the Snickerdoodle configuration. The configuration of the FPGA pins can (and will often) include routing/multiplexing logic, logical processing and hardware acceleration to be done using the FPGA. Each connector has 25 reconfigurable I/O as well as 1 ADC input and one I2C config port.
As described in Chapter 1 , the connectors can be configured as top-facing male headers (TFM) or bottom-facing female headers (SFM). Table 2.2 shows some important details of the connectors.
TODO: insert Table 2.2
Figure 2.5: FPGA Connectors (JC1 shown unloaded)
3. Power Supplies
WarningBox: Plugging Snickerdoodle into a power source that does not conform to the electrical requirements can damage the Snickerdoodle.
Snickerdoodle can be powered directly through the USB micro-B connector (J1) or through power input pins located on J2. When plugging Snickerdoodle into USB power, the power source should provide adequate electrical current for the application. When connected through the power input pins on J2 (pins 29 and 30), the input source should supply between +3.7V and +17V.
Each FPGA connector has a +3.3V reference tied to pin 1 and the PS connector has a +1.8V signal reference tied to pin 1. Snickerdoodle can be configured to drive a variety of electronic circuits. Driving signals originating from Snickerdoodle should be connected to high impedance inputs and not used as a power source. The signals coming from Snickerdoodle can be used to control a variety of electronic circuits including motor controllers and charge circuits.
High performance applications should be connected through J2 with a maximum of 3.2A per power supply pin. A +12V supply is recommended for very high performance applications. The +1.8V source on J2 will supply a total of 0.5A to connected devices/accessories. The +3.3V outputs on the FGPA connectors (JA1, JA2, JB1, JB1 and JC1) are able to supply a total of 1A to connected devices/accessories.
Programmable Logic Power (VCCO_xx)
WarningBox: Do not connect different power supplies to the logic power pins on connectors on the same bank. For example, do not attempt to connect a +1.8V supply to JA1 and a +3.3V supply to JA2.
The programmable logic power should be provided on pin 3 on the FPGA connectors. The power supply is shared between connectors on the same bank (i. e., JA1 and JA2, JB1 and JB2). For +1.8V interfaces, the on-board +1.8V source can be used as a supply to VCCO_xx. Similarly, the on-board +3.3V source can be used for +3.3V interfaces.
4. Zynq AP SoC Architecture
The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS), and the Programmable Logic (PL). Figure 3 shows an overview of the Zynq AP SoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and Multigigabit transceivers are not available on the Zynq7010 device.
Common specifications between the Z-7010 and the Z-7020:
TODO: insert Table 4.1
TODO: insert Table 4.2
5. Zynq Configuration
The hardware architecture of the Zynq allows full control of the FPGA fabric through then processing subsystem. The processor acts as a master to the programmable logic so that the state of the SoC and the boot process is not dependent on the FPGA configuration. In fact, the FPGA bitstream does not need to be defined prior to booting the device. This makes the boot process more similar to a microcontroller than an FPGA. A boot image is loaded and executed upon startup which loads a First Stage Bootloader (FSBL), an optional bitstream for configuring the programmable logic and, finally, a user-defined processing subsystem application or operating system.
The boot process is typically defined by a primary boot loader such as UBoot which is responsible for initiating each stage of the boot process. The stages of the boot process are as follows:
Step 1: Upon startup or reset, one of the processing cores executes a set of code from read-only memory (ROM) which initiates the boot process. The ROM is responsible for initiating processing of the first stage boot loader (FSBL) from a designated set of non-volatile memory (e. g., microSD card, flash). The FSBL should be included in a Zynq Boot Image which contains the data for the remaining boot process stages.
Step 2: Once the boot process is handed off to the FSBL, it configures the processing system and loads a bitstream to configure the programmable logic (if a bitstream exists within the boot image). The FSBL then loads any user-defined application/system into memory and prepares to finish the boot process.
Step 3: The user application/system is loaded during the final stage of the boot process. During this stage a secondary boot loader can be used to load a operating system (most commonly Linux) or a user defined application can be directly loaded by the FSBL. For a more thorough explanation of the boot process, refer to Chapter 6 of the Zynq Technical Reference Manual (latest, v1.10).
TODO: insert Table 5.1
Snickerdoodle can be booted using three difference sources. Table 5.1 shows the boot mode configuration pins that can be used to specify the boot source. The specific configuration pins for determining the three available boot sources are shown in Table 5.2 (MIO [4:5]).
TODO: insert Table 5.2
The boot mode can be configured wirelessly, through the krtkl app.
The most common way to boot Snickerdoodle is from a microSD card installed in J6 (described in more detail in Chapter 7 ). The microSD card slot provides a removable, upgradable, high-volume source of non-volatile storage from which a range of projects can be loaded. A microSD card can easily be loaded with a boot image that provides a small user application or a general purpose operating system such as Linux. A microSD card can be created and loaded with a bootable image by following a process described in Chapter 22 .
Snickerdoodle has a 16Mbyte quad-SPI NOR flash (Micron N25Q128A11ESE40F). The flash memory can be used to provide non-volatile storage of data and program code. The flash can be used as general storage for initialization of the processing subsystem as well as configuration of the FPGA by storing bitstream data that has been wrapped in a bootable image as described in Chapter 5 .
A JTAG connection can be made through J2 where the signals have been made available on pins 17-26, as shown in Table B.1 . These connections can be accessed directly from J2 or broken out when Snickerdoodle is mounted on a baseboard. The JTAG connection can be used to boot Snickerdoodle when connected to a host computer.
Because of the common JTAG interface the PL system can be configured using a JTAG connection without interfering with the processor.
6. DDR Memory
Micron® 8Gb mobile low-power DDR2 SDRAM (LPDDR2). The following tables record the parameters specified in the DDR Configuration of the ZYNQ7 Processing Systemwithin Vivado.
TODO: insert Table 6.1, 6.2, 6.3
7. microSD Slot
CautionBox: Make sure the microSD card cage is securely latched before powering your Snickerdoodle
The microSD card cage (J6) on Snickerdoodle provides a compact, locking connector for non-volatile storage of up to 200 GB. The microSD interface uses an SDIO interface that is connected to MIO Bank 501 pins 40-45 (SDIO 0). The microSD slot provides a source for non-volatile storage. The Zynq processing subsystem can be booted from the microSD connection and, optionally, a logic bitstream can be defined. For information on creating a bootable microSD card, refer to Chapter 22 .
TODO: insert Figure 7.1
The microSD card interface supports microSD cards of various speeds with a maximum clock frequency of 50MHz. High speed cards (Class 10) are recommended when using the microSD card as the boot device.
Snickerdoodle provides Wi-Fi and Bluetooth/BLE connectivity using a Texas Instruments WiLink™8 certified RF transceiver module.
TODO: insert Table 8.1
Both modules support IEEE 802.11b/g/n standards, Bluetooth 4.0 and Bluetooth low energy; providing Snickerdoodle with a variety of connectivity options. Figure 8.1 shows the location of the UFL jack that can be used to connect an antenna to Snickerdoodle.
TODO: insert Figure 8.1
9. Platform Controller (STM32)
Snickerdoodle has an STM32F0 series 32-bit ARM®Cortex-A0® microcontroller connected to and in control of various signals. The platform controller connects to the
The STM32 is connected to the Zynq through multiple communication buses. Each communications bus provides a message channel to/from the platform controller and can be used to provide access (through firmware) to the various platform controller peripherals.
J1 carries USB signals to/from the platform controller. The platform controller firmware allows the UART interface between the Zynq and STM32 to be bridged with the USB interface to a host computer. This is most commonly used as an interface to the Linux console. The serial console can be set up to interact with any user-defined application/system; most commonly to display Linux console data. The firmware required to create the bridged connection is described in greater detail in Chapter 16 .
TODO: insert Table 9.1 and 9.2
The SPI interface between provides a high-speed interface between the Zynq and platform controller. The interface can be used to provide the Zynq with access to control over the various peripherals and connections on the platform controller (e. g., LEDs, DACs, nINTs).
Two I2C interfaces on the platform controller are configured. The first I2C interface (designated I2C1) is connected to a switch which has the ability to independently communicate over the I2C pins on each of the 7 in-board connectors. The second interface (designated I2C2) is connected to an on-board crypto-authentication device. The crypto-authentication device can be used for several purposes including wireless network security, IoT network authentication and IP/software security.
External I2C Switch Interface (I2C1)
The STM32 is connected to an I2C switch that provides distribution of I2C connectivity to the connectors.
The STM32 is connected to the crypto-authentication device through an I2C interface. The crypto-authentication device is described in more detail in Chapter 10 .
The STM32 is connected to the Bluetooth UART interface on the Wilink 8 module.
The platform controller is connected to the SPI flash through an SPI interface. The SPI flash is normally used by the Zynq to boot Linux or store application data. Access to the SPI flash should be restricted to a single controller at a time. For example, the platform controller can be used to write a system to the SPI flash and then enable the Zynq to boot from the flash, after which the platform controller should not attempt to access the flash.
Each FPGA connector has an external interrupt pin connected to the platform controller. These interrupt pins can be used to drive interrupt routines to monitor and handle device connections.
Two timer peripherals on the platform controller are connected to the five on-board LEDs. The timers are configured as PWM outputs to give brightness control over the LEDs and allow a variety of LED patterns.
- Power/USB : Indicates input power and USB connectivity
- Fault : Indicates a board hardware fault
- Application : Can be used to indicate various software states
- Wireless/Link : Used to indicate wireless connection state
- Bluetooth : Indicates Bluetooth messages and states
The STM32 is connected to two user buttons that can be used to implement various functionality including boot configuration and interrupt based execution.
10. Crypto-Authentication Device
The crypto-authentication device provides mechanisms for securing the identity of a Snickerdoodle. The crypto-authenticator can be used for a number of applications including:
- Network Protection : Can create and support key agreements for message
encryption between network nodes.
- Checking User Password : Can be used to securely validate user passwords
and facilitate exchange of passwords between remote systems.
- Media/IP Protection : Can be used to validate the identity of a Snickerdoodle
for licensing of media or IP with anti-cloning protection.
The crypto-authentication device is an Atmel ATECC508A with the following features:
- Key Length: 256-bit
- Storage Size: Up to 16 keys
- Serial Number: Guaranteed unique 72-bit
- EEPROM: 10Kb memory
- Hash Algorithm: SHA-256